As BGA pitches shrink below 0.8 mm and board real estate becomes scarcer, the decision between High Density Interconnect (HDI) and Ultra HDI (UHDI) PCB technology has never been more consequential. Select the wrong process and you either over-engineer a commodity design adding unnecessary cost or under-specify a board that will fail to route in production. This guide gives engineers and procurement teams the technical depth to make the right call.
The global HDI PCB market was valued at approximately $16.2 billion in 2024 and is projected to reach $24.8 billion by 2029, driven by demand from defense, medical, automotive, and 5G telecommunications sectors. Ultra HDI is the fastest-growing segment of that market and American Standard Circuits is a leading North American manufacturer of advanced PCB technologies.
What Is HDI (High Density Interconnect)?
HDI PCBs use microvias, blind and buried vias, and finer copper routing to achieve higher interconnect density than conventional boards. The fabrication process is subtractive: a full copper layer is deposited, a photoresist pattern is exposed, and unwanted copper is chemically etched away. What remains are the traces.
The practical limit of subtractive etch is 50–75 microns (2–3 mil) for trace width and spacing. Below that threshold, undercut from the etchant becomes uncontrollable, trace profiles become trapezoidal, and yield drops sharply. Microvias in standard HDI typically range from 100–150 microns.
HDI is categorized into stack types 1+N+1 (one microvia layer each side), 2+N+2, and so on. As via layers increase, board complexity, lamination cycles, and cost increase proportionally. See ASC’s Design Guidelines for stack-up planning support.
What Is Ultra HDI (UHDI)?
Ultra HDI uses a Semi-Additive Process (SAP) rather than subtractive etch. Instead of depositing and removing copper, SAP starts with an ultra-thin seed layer and selectively grows copper only where it is needed, using precisely controlled electroplating.
ASC’s proprietary A-SAP™ (Advanced Semi-Additive Process) achieves line widths and spaces down to 20 microns (0.8 mil) in production today, with 12.5-micron (0.5 mil) capability emerging. This is a 2.5–5× improvement in trace resolution over standard HDI, and it fundamentally changes what is achievable in a given board footprint.
Critically, A-SAP™ at ASC uses a sub-1-micron layer of liquid ink as the seed conductor enabling feature sizes that mSAP and amSAP processes (which use 2–9 micron base copper layers) cannot reliably achieve. Learn more on ASC’s Ultra HDI product page.
Technical Comparison
|
Parameter |
HDI (Subtractive Etch) |
Ultra HDI, ASC A-SAP™ |
|
Min. Line Width / Space |
50–75 μm (2–3 mil) |
20 μm (0.8 mil); 12.5 μm emerging |
|
Process |
Subtractive copper etch |
Semi-Additive Process (SAP) |
|
Seed Layer |
3–9 μm base copper |
Sub-1 μm liquid ink conductor |
|
Microvia Size |
100–150 μm typical |
Down to 75 μm, copper-filled |
|
Trace Aspect Ratio (H:W) |
< 1:1 (trapezoidal cross-section) |
> 1:1 (rectangular, taller than wide) |
|
Impedance Tolerance |
±10% typical |
< ±5% achievable |
|
Signal Loss (high freq.) |
Higher conductor loss |
Lower conductor loss |
|
Layer Count for Same Density |
More layers required |
Fewer layers, direct cost reduction |
|
Lamination Cycles |
Higher (more layers = more cycles) |
Fewer cycles, less thermal stress |
|
Biocompatible Conductors |
Limited |
Yes, gold and noble metal traces |
|
Applies to Flex/Rigid-Flex |
Yes |
Yes, all board types (ASC A-SAP™) |
|
Hybrid Stack-up (mixed layers) |
Not applicable |
Yes, UHDI + subtractive in same board |
KEY DIFFERENTIATOR
ASC’s A-SAP™ process uses a proprietary sub-1-micron liquid ink seed layer, thinner than any mSAP or amSAP process. This enables 20-micron features that competing semi-additive approaches cannot consistently achieve, and eliminates the copper thickness variability that limits yield at fine geometries.
Signal Integrity: Why Trace Geometry Matters
One of the most underappreciated advantages of UHDI is its impact on signal integrity independent of feature size. It begins with trace cross-section geometry.
In subtractive etching, the chemical etching process attacks the trace from the sides as well as beneath the resist. The result is a trapezoidal trace: wider at the top, narrower at the bottom. This inconsistency creates variation in effective impedance along the trace length and makes it impossible to hold tolerances tighter than approximately ±10%.
In ASC’s A-SAP™ process, copper is grown upward from the seed layer. Traces are formed additively, not by removal, producing a near-rectangular cross-section with an aspect ratio greater than 1:1 (height exceeds width). The result:
• More consistent impedance profile along the trace length
• Lower conductor loss at high frequencies due to reduced skin-effect surface area variation
• Impedance tolerance under ±5% critical for RF/microwave and high-speed digital designs
• Better performance at mmWave frequencies where subtractive traces introduce measurable loss
For designers working on RF/microwave PCBs, ASC’s UHDI technology delivers measurable SI improvements over subtractive etch even at standard feature sizes. Signal integrity benefits are not limited to fine-line layers.
ENGINEERING NOTE
A-SAP™ signal integrity benefits apply even at 3-mil (75 μm) traces. If your design requires <±5% impedance control at any trace width, Ultra HDI processing is worth evaluating, not just for fine-line breakout layers. Ask ASC’s engineering team to model the SI delta for your specific design.
Cost Tradeoffs: The Full Picture
The most persistent misconception about Ultra HDI is that it is simply more expensive. The reality is layered and in many high-density design scenarios, UHDI delivers a lower total board cost.
Where Ultra HDI Processing Can Add Cost
• A-SAP™ chemistry, tooling, and process control carry a higher per-layer cost than commodity subtractive etch lines
• Initial DFM (Design for Manufacture) review may require more iteration for first-time UHDI programs
• For simple boards that don’t require fine lines, SAP adds complexity with no proportional benefit
Where Ultra HDI Reduces Total Cost
• Fewer layers: Layer count is the primary cost driver on complex multilayer PCBs. UHDI enables the same routing density with fewer layers reducing base material, inner-layer processing, and lamination cycle cost directly
• Fewer lamination cycles: Each sequential lamination step adds cost, cycle time, and cumulative thermal stress. Fewer layers means fewer press cycles
• Reduced microvia stacking: Stacked and staggered microvias are a significant yield risk and cost driver in deep HDI designs. UHDI’s finer routing reduces dependence on stacked via structures
• System-level savings: Smaller, lighter boards reduce downstream assembly cost, enclosure cost, and bill-of-materials cost for connectors and cabling
• Reliability improvement: Fewer lamination cycles mean fewer opportunities for delamination, CTE stress fatigue, and interlayer reliability failures
COST RULE OF THUMB
If UHDI allows you to reduce a design from 10 layers to 6 layers, the savings in base material, inner-layer processing, and lamination typically fully offset the higher per-layer A-SAP™ cost. The crossover point depends on the specific design, but for high-density boards with BGAs under 0.8 mm pitch, Ultra HDI is frequently cost-competitive or cheaper on a total-board basis.
Per ASC’s Ultra HDI product page: “Semi-additive processes have the potential to lower costs. One primary benefit of Ultra HDI is the ability to reduce layer count, which directly reduces base material, lamination cycle, and processing costs”.
Applications: When to Use Each Technology
The correct choice depends on design density, BGA pitch, performance requirements, and end application. Below is an application-level comparison:
|
Standard HDI — Best For |
Ultra HDI (A-SAP™) — Best For |
|
Commercial electronics with ≥ 0.8 mm BGA pitch |
BGAs with < 0.8 mm pitch requiring fine-line breakout |
|
Industrial controls with moderate routing density |
Military & aerospace electronics (SWaP-critical) |
|
Cost-sensitive high-volume consumer products |
Medical implantables & wearables (miniaturization + biocompat) |
|
Telecom equipment with conventional packages |
RF/Microwave designs requiring <±5% impedance control |
|
Designs already DFM-qualified at 2+ mil traces |
Designs where reducing layer count improves reliability & cost |
|
Programs using qualified subtractive etch suppliers |
Package substrates, interposers, IoT & wearable devices |
UHDI is particularly transformative in Flex and Rigid-Flex PCBs for medical wearables and aerospace applications, where fine-line routing, weight savings, and mechanical flexibility must coexist in a single board technology. ASC’s A-SAP™ is available on all board types and all material types.
Quick Decision Checklist
Use this reference to assess which technology fits your program:
|
Design Condition |
Use HDI |
Use Ultra HDI |
|
BGA pitch ≥ 0.8 mm, moderate routing density |
✓ |
|
|
BGA pitch < 0.8 mm, congested routing at current layer count |
|
✓ |
|
Impedance tolerance requirement ≤ ±5% |
|
✓ |
|
Size & weight reduction is a primary design goal |
|
✓ |
|
Medical design requiring biocompatible gold traces |
|
✓ |
|
High-volume commercial, cost-sensitive, simple routing |
✓ |
|
|
Defense/aerospace — layer reduction improves reliability |
|
✓ |
|
Some layers need fine lines; others do not (hybrid) |
|
✓ |
|
Design already validated and qualified at 2–3 mil |
✓ |
|
HYBRID APPROACH
The most cost-effective solution for many designs is a hybrid stack-up: A-SAP™ on signal layers requiring fine-line breakout, and standard subtractive etch on power and ground planes. ASC designs and fabricates hybrid boards routinely. Both subtractive-etch and SAP layers can coexist in the same PCB stack-up all layers do not need to be the same technology.
ASC’s Ultra HDI Capabilities (A-SAP™)
American Standard Circuits is one of North America’s leading producers of Ultra HDI PCBs. Our proprietary A-SAP™ process is backed by deep process expertise from John Johnson, ASC’s Ultra HDI technology director and a pioneer in ultra-fine line PCB development.
|
A-SAP™ Specification |
ASC Current Capability |
|
Min. Line Width / Space (Production) |
20 μm (0.8 mil) |
|
Min. Line Width / Space (Emerging) |
12.5 μm (0.5 mil) |
|
Seed Layer Thickness |
Sub-1 micron liquid ink conductor |
|
Minimum Microvia Diameter |
75 μm (copper-filled) |
|
Impedance Tolerance |
< ±5% |
|
Trace Aspect Ratio |
> 1:1 (rectangular profile) |
|
Board Types Supported |
Rigid, Flex, Rigid-Flex |
|
Material Compatibility |
All standard and specialty materials |
|
Hybrid Stack-ups |
Yes, SAP + subtractive etch in same board |
|
Outer Layer UHDI |
Yes, including plated through holes |
|
Biocompatible Conductors |
Yes, gold and noble metal traces available |
|
Certifications |
AS9100, ISO 9001, ITAR, DFARS, MIL-PRF-31032 |
UHDI reduces circuit size, reduces layer count, reduces lamination cycles, reduces microvia layers, and increases electronics functionality within existing footprints. Learn more about the A-SAP™ process in ASC’s webinar series at asc-i.com/resources/webinars.
Ready to Evaluate Ultra HDI for Your Next Design?
Contact ASC’s engineering team to discuss your design, request DFM guidance, or download the UHDI Capability Brochure.
Request a Quote | Contact Sales | View UHDI Capabilities | Browse ASC Webinars
Frequently Asked Questions
HDI uses subtractive etch to achieve 50–75 micron trace widths. Ultra HDI uses a semi-additive process (SAP) to achieve 20 microns or below enabling far greater routing density, fewer layers, and better signal integrity from the same board footprint.
Not on a total-board basis. The A-SAP™ per-layer processing cost is higher, but Ultra HDI typically reduces total cost by enabling fewer layers, fewer lamination cycles, and simpler stack-ups. For BGAs under 0.8 mm pitch, total UHDI cost is often comparable to or lower than a deeper HDI stack-up.
No. ASC routinely produces hybrid boards where only signal layers requiring fine-line breakout use A-SAP™ processing, while power and ground planes use standard subtractive etch. This is the most cost-effective approach for most programs.
Yes. ASC’s A-SAP™ process is available on rigid, flex, and rigid-flex board technologies across all material types, a significant advantage over processes that only work on rigid substrates. See ASC’s Flex/Rigid-Flex page for more.
Current production capability is 20 microns (0.8 mil) line and space. 12.5-micron (0.5 mil) capability is in development. Contact ASC to discuss your specific program requirements.
Yes. The rectangular trace cross-section produced by A-SAP™ delivers lower conductor loss at high frequencies and tighter impedance control than subtractive etch both critical for RF/Microwave PCBs. UHDI is also enabling new approaches to metal-backed RF PCBs for defense radar and EW applications.