Ultra High Density Interconnects

Q: Can A-SAP™ processes also produce larger feature sizes?

A: Yes. A-SAP™ is not just for ultra HDI. There are signal integrity benefits to semi-additive processes that make it preferable for larger feature sizes as well.

Q: Do all layers of a board need to be produced with these ultra-high density feature sizes?

A: No. Both subtractive-etch layers and A-SAP™ layers can be used in the same PCB stack-up. All layers do not have to be the same technology: a hybrid approach is most common. Typically, signal layers will utilize A-SAP™ technology to simplify the breakout of smaller BGA packages, reducing the number of layers and lamination cycles required. For layers that contain only larger feature sizes, traditional subtractive-etch technology can be used.

Q: Can outer layers and plated through holes be created with A-SAP™?

A: Yes. You can confidently design a PCB with ultra-HDI features on outer layers and connect with reliable plated through holes, using the A-SAP™ process.

Q: What is the maximum number of layers and number of lamination cycles for A-SAP™technology?

A: There is actually no limit.

With the smaller features, it makes sense to focus on designs that can increase reliability by minimizing stacked vias. This avoids additional cost resulting from processing the stacked structure.

Ideally, the use of ultra-fine lines should also focus on the elimination of microvia structures, especially multiple stacked microvias, to minimize reliability issues from stacked microvias and the additional cost resulting from processing the stacked structures.

Q: What is the minimum spacing from trace to pad (external layer)?

A: That depends on how pads are defined by soldermask-  If pads are mask defined, spacing can be as low as 25 micron.  If defined by the copper, then other features need to be at least 50 microns away, preferably 75 microns.

The copper to copper spacing can add costs in subtractive etch processes.  In the semi-additive environment, this is not the case.

1. On inner layers, spacing could be 25 microns or below.
2. For outer layers, there must be enough space to allow the soldermask to fully cover the trace and not expose any copper.  If the mask defines the pad, the coverage is not an issue so 25 micron can work.  If not, mask registration allowances need at least 50 micron spacing or more.

Q: Reliability: are PCBs made with A-SAP™ as reliable as those fabricated with traditional processes?

A: Yes. The Averatek Semi-Additive Process (A-SAP™) is a proven and tested additive fabrication method to achieve next-generation advancements. Contact us for more information.

Q: Cost: how does A-SAP™ compare to subtractive etch?

A: A-SAP™ has potential to lower costs. One primary benefit of ultra HDI is the ability to reduce layer count, reduce lamination cycles and reduce the complexity of the PCB design. While A-SAP™ processing costs can be higher than subtractive etch, the overall simplification of the design may reduce total costs or provide added functionality within a similar cost structure.

Q: What are design considerations when designing with Via-In-Pad-Plated-Over (VIPPO)?

A: Via-in-pad structures should be run on non-A-SAP™ layers.  If needed, these structures should be used in an external mixed power/ground structure with limited traces and line widths of 3 mils with 5 mil spacing.

• If via-in-pad is necessary along with ultra-fine lines: a copper-filled microvia should be used to route to the next layer down. This via should be 3 to 4 mils diameter, and the dielectric spacing should be no greater than the via diameter, preferably less - aspect ratio 1:1 max.
• If top and bottom layers of the subassembly do not require ultra-fine line width technology: a buried via structure may be used.  This via may be filled and plated over.