Ultra High Density Interconnects
ASC is a North American electronics industry leader in developing and implementing technology for PCBs needing ultra high density interconnects.
An early licensee of Averatek Corporation’s patented A-SAP™ Technology, ASC can produce Ultra-Fine Lines and Spaces in any board technology- Rigid, Flex and Rigid-Flex needing line widths down to 25 micron. Later in 2023 ASC will further step down into the 15 micron range.
ASC licenses Averatek Corporation’s Semi-Additive Process (A-SAP™) and uses it as a unique fabrication technique to manufacture ultra-fine line trace and space in ASC’s Ultra High-Density Interconnect program.
Design advantages include:
- Dramatic size and weight reduction over current state-of-the-art {Currently ASC builds down to 20 micron (0.8 mil) trace and space with 12.5 micron (0.5 mil) trace and space available later this year}
- Tight spacing and impedance control (< 5%) for all line widths, including 3 mils and above
- Reduced layer count, micro vias and lamination cycles – for greater reliability
- Aspect ratios greater than 1:1 for metal traces – for improved signal integrity
- RF performance better than traditional subtractive-etch processes
- Biocompatibility – gold and other noble metals can be used as conductive materials, no copper or nickel needed
- Reduced costs - especially for complex, high-performance boards
- Works with a wide variety of materials
- Dramatic size and weight reduction over current state-of-the-art
- Improved Reliability: reduced layer count, micro vias and lamination cycles
- Improved Signal Integrity
- Aspect ratios greater than 1:1 for metal traces
- Improved RF performance over standard subtractive process
- Biocompatibility advantages: Use gold as conductive metal- eliminate copper and nickel
FAQ
Q: Can A-SAP™ processes also produce larger feature sizes?
A: Yes. A-SAP™ is not just for ultra HDI. There are signal integrity benefits to semi-additive processes that make it preferable for larger feature sizes as well.
Q: Do all layers of a board need to be produced with these ultra-high density feature sizes?
A: No. Both subtractive-etch layers and A-SAP™ layers can be used in the same PCB stack-up. All layers do not have to be the same technology: a hybrid approach is most common. Typically, signal layers will utilize A-SAP™ technology to simplify the breakout of smaller BGA packages, reducing the number of layers and lamination cycles required. For layers that contain only larger feature sizes, traditional subtractive-etch technology can be used.
Q: Can outer layers and plated through holes be created with A-SAP™?
A: Yes. You can confidently design a PCB with ultra-HDI features on outer layers and connect with reliable plated through holes, using the A-SAP™ process.
Q: What is the maximum number of layers and number of lamination cycles for A-SAP™technology?
A: There is actually no limit.
With the smaller features, it makes sense to focus on designs that can increase reliability by minimizing stacked vias. This avoids additional cost resulting from processing the stacked structure.
Ideally, the use of ultra-fine lines should also focus on the elimination of microvia structures, especially multiple stacked microvias, to minimize reliability issues from stacked microvias and the additional cost resulting from processing the stacked structures.
Q: What is the minimum spacing from trace to pad (external layer)?
A: That depends on how pads are defined by soldermask- If pads are mask defined, spacing can be as low as 25 micron. If defined by the copper, then other features need to be at least 50 microns away, preferably 75 microns.
The copper to copper spacing can add costs in subtractive etch processes. In the semi-additive environment, this is not the case.
- On inner layers, spacing could be 25 microns or below.
- For outer layers, there must be enough space to allow the soldermask to fully cover the trace and not expose any copper. If the mask defines the pad, the coverage is not an issue so 25 micron can work. If not, mask registration allowances need at least 50 micron spacing or more.
Q: Reliability: are PCBs made with A-SAP™ as reliable as those fabricated with traditional processes?
A: Yes. The Averatek Semi-Additive Process (A-SAP™) is a proven and tested additive fabrication method to achieve next-generation advancements. Contact us for more information.
Q: Cost: how does A-SAP™ compare to subtractive etch?
A: A-SAP™ has potential to lower costs. One primary benefit of ultra HDI is the ability to reduce layer count, reduce lamination cycles and reduce the complexity of the PCB design. While A-SAP™ processing costs can be higher than subtractive etch, the overall simplification of the design may reduce total costs or provide added functionality within a similar cost structure.
Q: What are design considerations when designing with Via-In-Pad-Plated-Over (VIPPO)?
A: Via-in-pad structures should be run on non-A-SAP™ layers. If needed, these structures should be used in an external mixed power/ground structure with limited traces and line widths of 3 mils with 5 mil spacing.
- If via-in-pad is necessary along with ultra-fine lines: a copper-filled microvia should be used to route to the next layer down. This via should be 3 to 4 mils diameter, and the dielectric spacing should be no greater than the via diameter, preferably less - aspect ratio 1:1 max.
- If top and bottom layers of the subassembly do not require ultra-fine line width technology: a buried via structure may be used. This via may be filled and plated over.
UHDI Capabilities
- 25 micron lines and spaces- sub 25 micron coming soon!
- Available on board types- Rigid, Flex and Rigid-Flex.
- Available on all material types.
- Hybrid constructions using Ultra Fine line features on select layers; standard technology on others.
- Microvias to 75 micron with copper filling.
- Tight Impedance tolerances and improved signal integrity.
Your expert for Ultra High Density Interconnect is John Johnson
John has a long tenure in Material and Printed Circuit manufacturing. After obtaining an Masters of Science in Organic Chemistry from The Ohio State University, he has held positions as an R&D Chemist, Quality Engineer, Sr. Process Engineer, Quality Manager, Sales Rep, Director of Sales, General Manager, President/CEO. Prior to joining ASC as a Director of Business Development, he was VP of Sales and Customer Support at Averatek Corp and focused on Ultra Fine Line technology.
John is currently serves as ASC’s Director of Quality and is ASC’s Technology Expert on Ultra High Density Interconnects.